Hardware Implementation of an Analog Accumulator for On-chip BP Learning Neural Networks

摘要：

An analog accumulator is proposed in this paper. It is used in an on-chip BP (Back-Propagation) batch learning neural network. The proposed circuit has been fabricated with 1.2-μm CMOS, double-polysilicon, double-metal technology. Experiment results show that the circuit achieves the analog accumulation function.

作者: Chun Lu Bing-xue Shi Lu Chen

作者单位: Institute of Microelectronics, Tsinghua University Beijing 100084, China

会议类型: 国际会议

会议名称: 8th International Conference on Neural Information Processing(ICONIP 2001)(第八届国际神经信息处理大会)

会议地点: 上海

会议语种:英文

页码: 1245-1248

在线出版日期: 2001-11-14（万方平台首次上网日期，不代表论文的发表时间）