Fluctuating Power Logic (FPL): A constructive SCA resistant scheme at transistor level
Hiding and masking are two mainstream countermeasures against side channel analysis (SCA) at cell levels.In power analysis, both rely on the fact that variant data transitions consume more distinguishable power than invariant ones.In this letter, we propose a novel scheme based on fluctuating power logic (FPL), which mitigates the side-channel effect by employing cascade voltage logic to fluctuate physical power leakages.This proposed scheme is illustrated by a standard flip-flop which typically behaves as a major power consumer of the circuit.HSPICE based simulation shows that the modified flip-flop is resistant against power analysis at the cost of doubled power dissipation.Our proposal can be further applied to enhance various SCA-resistant logics, such as sense-amplifier based logic (SABL) and wave dynamic differential logic (WDDL).
low power flip-flop clock-gating scheme dual-edge
Fan Zhang Liang Geng Congyuan Xu Jizhong Shen Xinjie Zhao Shize Guo
College of Information Science & Electronic Engineering, Zhejiang University,Hangzhou, 310027, China College of Information Science & Electronic Engineering, Zhejiang University,Hangzhou, 310027, China Science and Technology on Communication Security Laboratory, Chengdu, 610041,China The Institute of North Electronic Equipment, Beijing, 100000, China
国内会议
北京
英文
118-126
2016-08-29（万方平台首次上网日期，不代表论文的发表时间）