Design of a Digitally Controlled Oscillator in All Digital Phase Locked Loop

摘要：

　　This paper presents a LC digitally controlled oscillator (LC-DCO) applied in all digital phase locked loop (ADPLL).Post-layout simulation is finished in a 130nm CMOS process to design and verify the DCO.It is operated between 3.27GHz and 4.40GHz, for a 31% tuning range.Drawing 3.8mA from 1.2V, the phase noise is -135.4dBc/Hz at a 3MHz offset from a 3.27GHz carrier.The resulting phase phase-noise FoM is 189.6dBc/Hz a 3MHz offset from a 3.27GHz carrier.

作者: Lei Ma Junhui Xiang Hao Min

作者单位: ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China

会议类型: 国内会议

会议名称: 2016年上海市研究生学术论坛——电子科学与技术

会议地点: 上海

会议语种:英文

页码: 151-154

在线出版日期: 2016-04-01（万方平台首次上网日期，不代表论文的发表时间）