A Low Power TDC with 0.5ps Resolution for ADPLL in 40nm CMOS

摘要：

　　A low power time-to-digital converter (TDC) with high resolution is presented in this paper.The TDC employs a digital-to-time converter (DTC) to reduce the dynamic range based on a phase-prediction technique.A snapshot circuit is used to reduce the sampling rate from digitally-controlled oscillator (DCO) frequency to reference frequency.In addition, the proposed digital architecture adopts a time-amplifier based TDC (TA-TDC) to achieve high resolution.The proposed TDC is implemented in SMIC 40nm CMOS.Simulation results show that it can achieve a resolution about 0.5ps while totally consuming only 163uW.

关键词： time-to-digital converter all-digital PLL digital-to-time converter time amplifier

作者: Xusong Liu Lei Ma Na Yan

作者单位: ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China

会议类型: 国内会议

会议名称: 2016年上海市研究生学术论坛——电子科学与技术

会议地点: 上海

会议语种:英文

页码: 250-253

在线出版日期: 2016-04-01（万方平台首次上网日期，不代表论文的发表时间）