Improvement of Shipped Product Quality Level for Logic VLSIs Based on Semiconductor Layout

摘要：

OUTLINE-Background-Critical Area Analysis-Weighted Fault Coverage-SPQL for Benchmark Circuits-Experimental Results from Renesas-Steiner Tree and Critical Area.

作者: Kazuhiko Iwasaki

作者单位: Tokyo Metropolitan University21st PRDC,Zhangjiajie,China

会议类型: 国内会议

会议名称: The 7th International Symposium on Parallel Architectures, Algorithms and Programming, PAAP2015(2015年第七届国际并行体系结构,算法和编程研讨会)

会议地点: 张家界

会议语种:英文

页码: 1-3

在线出版日期: 2015-11-18（万方平台首次上网日期，不代表论文的发表时间）