Modeling and Implementation of a Custom-designed High-Frequency Charge-Pump PLL
Phase Locked-Loop (PLL) is an essential component for many applications, e.g., wireless communications, high-performance microprocessors, whose performance determines the quality of signal processing in communication systems or microprocessors.This paper focuses on the modeling and implementation of a custom-designed charge-pump PLL ASIC.It gives a comprehensive analysis of the PLL and describes the tailored designs of a voltage-controlled oscillator (VCO), a phase-frequency-detector, a charge-pump, and other sub-components of the PLL.According to the SystemC-AMS model simulation and the post-layout simulation of the overall PLL design, it shows a stable and high-performance clock signal ranged from 400MHz to 1.2GHz is generated.
PLL VCO Charge-Pump SystemC-AMS
Guan Yongfeng Ding Wei Xu Tao He Xiaowei
National University of Defense Technology, Changsha, 410073, China China Defense Science and Technology Information Center, Beijing, 100142, China Army Aviation Plant Representative Office, Tijian, 300462, China
国内会议
贵阳
英文
290-296
2014-07-31（万方平台首次上网日期，不代表论文的发表时间）