Research on Latch-up Issue in the Chip-level ESD Power-up Test

摘要：

　　An IC-level electrostatic discharge (ESD) test method to test the power-up chip is introduced in this paper.The power-up ESD (PESD) test results can be classified into 3 grades: pass, latch-up and damage.In practical applications, the results of PESD are often worse than power-down ESD test.Latch-up is a peculiarly phenomenon in power-up test.During the test, the huge current in latch-up issue may lead to damage of the IC.The damage caused by latch-up issue is studied and the impact of power supply voltage on the latch-up issue is analyzed in this paper.

关键词： EMC ESD Latch-up PESD test I/O protection circuit

作者: Xu Chenghang Wu Jianfei Li Jiancheng Peng Ruijie Guo Yin

作者单位: National University of Defence Technology, Changsha 410073, China

会议类型: 国内会议

会议名称: 第十七届计算机工程与工艺年会暨第三届微处理器技术论坛

会议地点: 西宁

会议语种:英文

页码: 320-324

在线出版日期: 2013-07-20（万方平台首次上网日期，不代表论文的发表时间）