A 10-bit 2.5-MS/s SAR ADC with 60.46dB SNDR in 0.13-μm CMOS technology
This paper presents a low power 10 bit 2.5MS/s successive approximation register (SAR) analog to digital converter (ADC) design for intelligent signal process system of micro controller unit (MCU) in application of internet of thing (IoT).Because of the proposed new segmented architecture of 7 MSBs plus 3 LSBs capacitor resistor (C-R) hybrid digital to analog converter (DAC) using a thermometer decoder for the most significant 5 MSBs, this design achieves superior static nonlinearity and dynamic performance of SNDR, SFDR.Utilizing the proposed deviation calibration technique, the discharging and charging via substrate resulting from deviation of the comparator”s common-mode voltage is cancelled.The ADC is fabricated in a standard 1P5M 0.13μm CMOS technology.The peak DNL and INL are +0.18/-0.20 LSB,+0.30/-0.25 LSB respectively while the ENOB is 9.52 bit around all Process Voltage Temperature (PVT) comer analysis.At a 2.3-V supply voltage and a 2.5 MS/s sampling rate, the ADC achieves a SNDR of 60.46dB, SFDR of 75.32dB while the power dissipation is 0.191-mW, that resulting in a figure of merit (FOM) of 98.45fJ/c-s.The die of ADC measures 0.51×0.20mm2 resulting in area efficiency (AE) of 122.6μm2/code and compared with the benchmark SAR ADCs, this work is the most area efficient design.
Analog-to-digital-converter (ADC) Successive-approximation-register (SAR) Capacitor-Resistor (C-R) hybrid DAC Deviation calibration technique Thermometer decoder
Ruofan Dai Yunlong Zheng Zi Wang Hongwei Zhu Weiran Kong Shichang Zou
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Shanghai Huahong Grace Semiconductor Manufacturing Corporation State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and
国内会议
广州
英文
601-612
2015-05-01（万方平台首次上网日期，不代表论文的发表时间）