Efficient Multi-Rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard
An efficient rate-compatible encoder for IEEE 802.16e LDPC codes is proposed in this paper,which outperforms current single rate encoders with acceptable hardware consumption and efficient memory consumption.This design takes advantage of the common dual-diagonal structure in parity matrices to avoid the inverse matrix operation which requires extensive computations.Moreover,parallel MVM(Matrix-Vector Multiplication)units,bidirectional operation and storage compression are applied to this multi-rate encoder.The former two are utilized to increase encoding speed; while storage compression is used to significantly reduce the quantity of memory bits.In addition,the proposed encoding architecture is also contributed to a class of multi-rate encoders whose parity matrix is dual-diagonally structured and has an ALT(Approximately Lower Triangular)form,such as IEEE 802.11n and IEEE 802.22.Simulation results confirm that the proposed encoder can efficiently work for all code rates specified in WIMAX standard.With a maximum clock frequency of 118.13 MHz,the encoder achieves 3-8 times higher throughput than prior works.In other words,the designed encoder provides the ability to switch among six rates with the change of input parameter and achieves the throughput of approximately 1Gbps,making a good trade-off between rate capability and high throughput.
encoder multi-rate FPGA dual-diagonal WIMAX
Xiumin Wang Tingting Ge Fangfei Hong Jun Li
Department of Information Engineering,China Jiliang University,Hangzhou,China,310018 National Mobile Communications Research Laboratory,Southeast University Nanjing,China,210018
国内会议
第10届全国计算机支持的协同工作学术会议暨中国计算机学会协同计算专委年度工作会议
太原
英文
453-473
2015-08-28（万方平台首次上网日期，不代表论文的发表时间）