A Hybrid Aging Delay Model Considering PBTI and TDDB
Below 45nm process technique,the shrinking silicon feature size brings in high-k/metal gate which significantly exacerbates the Positive Bias Temperature Instability (PBTI) and Time-Dependent Dielectric Breakdown (TDDB) effect of NMOS transistor.However,previous works presented delay models to characterize PBTI or TDDB individually.This paper demonstrates that the delay caused by joint effect of PBTI and TDDB widely differs from the cumulated result of the delay caused by PBTI and TDDB respectively with the experiments on an inverter chain.This paper proposes a hybrid aging delay model comprising both PBTI and TDDB effect by analyzing the relationship between aging propagation delay and inherent delay of the gate.Experimental results on the logic gates under 45nm,32nm,22nm and 16nm CMOS technologies show that the maximum error between the proposed model and the actual value is less than 2.5%,meanwhile the average error is about 1.5%.
Circuit aging Positive Bias Temperature Instability Time-Dependent Dielectric Breakdown
Yong Miao Maoxiang Yi Guimao Zhang Dawen Xu
School of Electronic Science and Applied Physics Hefei University of Technology Hefei,Anhui Province, China
国内会议
成都
英文
1-5
2014-10-01（万方平台首次上网日期，不代表论文的发表时间）