Computational Modeling of Effects of Die Bonding Defect on the Junction Temperature Distribution of Flip-Chip LED
Flip-chip (FC) light-emitting diodes (LED) have been gaining increasing attention in current lighting industry for their prominent thermal performance and excellent light extraction efficiency.For an FC-LED,its active region is directly bonded to its sub-mount by a thin layer of solder alloy like gold-tin (Au-Sn) alloy or other tin base alloy.The bonding layer becomes the main heat dissipation path.The metal bonding is usually formed by thermal compression or reflow.Unfortunately,in the practical bonding process,defects can often be founded inside the bonding layer.In the reflow process,voids are very likely to be trapped inside the solder when flux is applied,meanwhile in the thermal compression process,some area may not be well bonded because of surface condition or co-planarity of the bonding pad.As a result,the junction of FC-LED on top of these defects lost its original heat dissipation path and might become a hot-spot.In this study,effects of these defects on steady-state thermal performance were investigated by finite element method (FEM).A 1 mm by 1 mm FC-LED was modeled.The LED chip was mounted on a silicon sub-mount.Different structure dimension were considered.And artificial voids were intentionally modeled inside the bonding layer.The simulation results indicate that void inside bonding layer will generate hot-spot in the LED junctio
国内会议
宜昌
英文
1-6
2014-05-15（万方平台首次上网日期，不代表论文的发表时间）