Protocol Aware ATE
Modern semiconductor devices often behave in a non-deterministic manner not only in their end application but during test execution on ATE as well．This is the result of design methodologies that allow the assembly of the device from a library of IP blocks．These IP blocks often support specific industry standard protocols such as JTAG，DDR memory buses，PCI Express，etc．While the operation of any individual block may be predictable the timing relationship between protocols often is not．Today’s SOC ATE does not deal well with ambiguity．Any deviation from expected device behavior will cause that device to fail ATE test，both during engineering development or production．Functionally testing devices that exhibit non-deterministic behavior is extremely difficult on current generation ATE．This paper describes a proposed solution to deal with non-deterministic device behavior，a new ATE architecture-Protocol Aware ATE(PA-ATE).Specifically covered will be some of the problems currently faced by Semiconductor ATE users and the usefulness of Protocol Aware ATE to address those problems．As described by Andy Evans of Broadcom，protocol Aware ATE is an：”ATE Architecture which can natively emulate real time chip I/O at the Protocol Level. Enables testing a device ”with methods” ranging from using a single chip interface to total ”Mission Mode”，at the highest level of abstraction centric to the interfaces specific protocols.”
半导体器件 议定书意识 测试架构协议
Eric Larson
Teradyne 30701 Agoura Road Agoura Hills，Calif USA 91301
国内会议
2008”北京微电子国际研讨会暨中国半导体行业协会集成电路设计分会年会
北京
英文
212-220
2008-10-28（万方平台首次上网日期，不代表论文的发表时间）