Producing the Smallest DRAM Cell Available to Date Through the Development and Implementation of 6F2 Array Architecture
As lithography progresses into the sub-100 nanometer (nm) realm, the capital investment and technology needed to achieve smaller DRAM cell and chip sizes-and therefore reduced cost per bit-can be formidable. A solution many memory companies are trying to develop is to scale the cell area factor from a typical value of 8 down to 6(F2) for a given feature size F. Micron is the first manufacturer to implement the 6F2 cell architecture into production-four years ahead of the industry timeline. Converting to 6F2 utilizes 25 percent less array space than conventionally manufactured 8F2 arrays, and boosts manufacturing efficiency by approximately 20 percent. This paper discusses a manufacturable 6F2 DRAM technology, showing scalability to at least 78nm half-pitch feature size that results in the smallest DRAM cell size (0.036 μm2) reported to date. The 6F2 cell design enables the simplification of photo and etch processes and maximizes the capacitor cell area. An MIM capacitor that employs composite high-k dielectric materials is integrated into the process. This novel cell technology is suitable for 2Gb-and 4Gb-density DRAM with a competitive die size for volume production.
芯片尺寸 复合材料 光刻技术
F. Fishburn L. Tran B. Busch J. Dale D. Hwang R. Lane T. McDaniel S. Southwick R. Turi H. Wang
Micron Technology, Inc. Boise, Idaho - USA Micron Technology, Inc. Boise, daho - USA
国内会议
上海
英文
288-290
2004-09-01（万方平台首次上网日期，不代表论文的发表时间）