Mapping of Irregular IP onto NoC Architecture with Optimal Energy Consumption
Network on chip (NoC) architectures have been proposed to resolve complex on-chip communication problems. An NoC-based mapping algorithm is shown in this paper. It can map irregular intellectual properties (IPs) cores onto regular tile 2-D mesh NoC architectures. The basic idea is to decompose a large IP into several dummy IPs or integrate several small IPs into one dummy IP, such that each dummy IP can fit into a single tile. It can also allocate buffer space according to the input/output degree and avoid connection congestion by adapting communication density. Experimental data indicate that using the algorithm proposed in this paper, the communication energy can be reduced about 7％.
network on chip (NoC) communication matrix router weight communication density
LI Guangshun WU Junhua MA Guangsheng
College of Computer Science and Technology,Harbin Engineering University,Harbin 150001,China;College College of Computer Science and Technology,Harbin Engineering University,Harbin 150001,China
国内会议
北京
英文
146-149
2007-07-15（万方平台首次上网日期，不代表论文的发表时间）