On-Chip Built-in Jitter Measurement Circuit for PLL Based on Duty-Cycle Modulation Vernier Delay Line
Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequency clock from an external lower frequency signal and its characterization and measurement have recently been calling for more and more attention. In this paper, a built-in on-chip circuit for measuring jitter of PLL based on a duty cycle modulation vernier delay line is proposed and demonstrated. The circuit employs two delay lines to measure the timing difference and transform the difference signal into digital words. The vernier lines are composed of delay cells whose duty cycle can be adjusted by a feedback voltage. It enables the circuit to have a self calibration capability which eliminates the mismatch problem caused by the process variation.
phase-locked loop (PLL) jitter vernier delay line duty-cycle modulation on-chip test
YU Fei Chung Len Lee ZHANG Jingkai
Institute of Microelectronics,Peking University Shenzhen Graduate School,Shenzhen 518055,China Department of Electronics Engineering,National Chiao Tung University,Hsin Chu,Taiwan,China
国内会议
北京
英文
128-133
2007-07-15（万方平台首次上网日期，不代表论文的发表时间）