On-Chip Multi-Giga Bit Cycle-to-Cycle Jitter Measurement Circuit
This paper presents an on-chip measurement circuit to measure multi-giga bit cycle-to-cycle jitter based on the vernier occillator (VO), which is inherited from the famous vernier delay line. The calibration method is also given. The circuit adopts a differential digital controlled delay element, which makes the circuit flexible in adjusting the measurement resolution, and a highly sensitive phase capturer, which makes the circuit able to measure jitters in pico-second range. The parallel structure makes it possible to measure consecutive cycle-to-cycle jitters. The performance of the circuit was verified via simulation with SMIC 0.18 urn process. During simulation under the clock with the period of 750 ps, the error between the measured RMS jitter and the theoretical RMS jitter was just 2.79 ps. Monte Carlo analysis was also conducted. With more advanced technology, the circuit can work better. This new structure can be implemented in chips as a built-in self-test IP core for testing jitter of PLL or other clocks.
jitter measurement cycle-to-cycle jitter vernier delay line vernier oscillator
ZHANG Jingkai Chung Len Lee TIAN Chao YU Fei
Institute of Microelectronics,Peking University Shenzhen Graduate School Shenzhen 518055,China Department of Electronics Engineering,National Chiao Tung University,Hsin Chu,Taiwan,China
国内会议
北京
英文
1-7
2007-07-15（万方平台首次上网日期，不代表论文的发表时间）