A 14-bit 2.5 GS/s DAC based on Multi-Clock Synchronization

摘要：

　　This paper presents a 14-bit 2.5GS/s current-steering segmented DAC with a new technology of synchronization, called multi-clock synchronization, which is used to optimize the timing between the internal digital and analog domains. The quad-switch architecture is also adopted to mask the code-dependent glitches. The full-scale output current can be programmed over the 10mA to 30mA range, and the typical full-scale output current is 20mA. The device is manufactured on a standard 0.18μm CMOS process and operates from 1.8V and 3.3V supplies.

关键词： Multi-clock synchronization quad-switch digital-to-analog converter

作者: Hegang Hou Zongmin Wang Ying Kong Xinmang Peng Haitao Guan Jinhao Wang Yan Ren

作者单位: Beijing Microelectronics Technology Institute, Beijing, China

会议类型: 国际会议

会议名称: 2015 Joint International Mechanical,Electronic and Information Technology Conference(JIMET 2015)(2015 联合国际机械,电子与信息技术国际会议)

会议地点: 重庆

会议语种:英文

页码: 939-944

在线出版日期: 2015-12-18（万方平台首次上网日期，不代表论文的发表时间）