A New Placement Approach to Minimizing FPGA Reconfiguration Data

摘要：

Dynamic reconfiguration for fine-grained architectures is still associated with significant reconfiguration costs. In this paper,a new placement algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. The algorithm is modified on the existing placement algorithm within VPR. It introduces the CLBs configuration of the previous circuit into cost function to increase similarity of CLBs configuration for subsequent circuits at the layout level. By using difference-based partial reconfiguration design flow,the proposed approach is validated by experiments on Xilinx Virtex FPGA platform,and experimental results show that the size of reconfiguration bitstream can be reduced.

作者: Weinan Chen Ying Wang Xiaowei Wang Chenglian Peng

作者单位: Department of Computing and Information Technology,Fudan University,Shanghai,China

会议类型: 国际会议

会议名称: The 2008 International Conference on Embedded Software and Systems Symposia(ICESS 2008)(2008国际嵌入式系统及嵌入式软件会议)

会议地点: 成都

会议语种:英文

页码: 169-174

在线出版日期: 2008-01-01（万方平台首次上网日期，不代表论文的发表时间）