An Optimization Method for Embarrassingly Parallel under MIC Architecture
Nowadays,heterogeneous architecture of CPU plus accelerator has become a mainstream in supercomputing.Intel lauched its Xeon Phi coprocessor in this context.It uses Intels many-core architecture,which greatly improves the single node parallelism.This paper studies the optimization of embarrassingly parallel programs under Intel MIC architecture,to maximize the utilization of CPU and Phi processor,and reduce the running time of parallel programs,by combining the computing power of CPU and Phi.This socalled embarrassingly parallel program often have doall main loops,that is,there are no dependencies between iterations,so they can be fully parallelized.This doall loop exists in many typical parallel programs.We come up with a loop allocation method for doall loops under this CPU/MIC architecture,to satisfy the above performance objectives.
exascale many-core embarrassingly parallel loop allocation performance tuning Intel Xeon Phi
Yunchun Li Xiduo Tian
Sino-German Joint Software Institute School of Computer Science and Engineering,Beihang University Beijing,China
国际会议
贵阳
英文
17-20
2015-08-18(万方平台首次上网日期,不代表论文的发表时间)