Numerical Study of Allowable Current Density for Electromigration Damage of Multilevel Interconnection in Integrated Circuit
The high current density occurring in integrated circuits induces electromigration (EM) of the metal lines used for electric wirings. A void is formed by EM in the line material and the growth of void leads to the line failure. Recently, multilevel interconnection is widely used in electronics devices and MEMS by connecting upper and lower metal lines through vias. The reservoir structure is often constructed in the multilevel interconnection. It is known that there is threshold current density of EM damage in multilevel interconnection with vias. It is important to evaluate the threshold for determination of allowable electric current in the interconnection. In this study, a numerical simulation technique for analyzing the atomic density distribution generated by EM in the line is applied to evaluate the EM risks of metal line in several kinds of the multilevel structures. The thresholds of current density leading to EM change were calculated through the simulations. We confirmed that the atomic density distribution in the line was essential to increase the threshold and to prevent EM damage in the line. And we also showed the simulation technique was useful in the design of safety structure of electric wirings in integrated circuits.
Integrated Circuit Reliability Electromigration Multilevel Interconnection Allowable Current Density
Kazuhiko Sasagawa Kazuhiro Fujisaki Takahiro Yanagi
Department of Intelligent Machines and System Engineering,Hirosaki University,Hirosaki,036-8561,Japan
国际会议
北京
英文
1-8
2013-06-16（万方平台首次上网日期，不代表论文的发表时间）