A High Robust SRAM Bitcell under Optimum-Energy Supply Voltage

摘要：

　　Simulation results illustrate that there is an optimum-energy supply voltage point (Vopt)for SoC.And these voltage points normally lie in weak sub-threshold or near-threshold region.Considering about the degraded robustness under this low supply voltage,structural change instead of the sizing change is considered in proposed design.Different from conventional 6T SRAM design,the trip point voltage of proposed design changes according to bit-line voltage values.In this way,its read margin is 45% greater than conventional 6T SRAM.The proposed bit-cell exhibits wide hysteresis effect,making the design less vulnerable to process variation.Its hold margin is 30.2% greater than conventional 6T SRAM.The optimum-energy supply voltage of proposed array (256x16) is 400 mV.At the same time,the power consumption at 400 mV decreases to 16%compared to that at 1200 mV.

关键词： SRAM low leakage current optimum energy-per-operation static noise margin

作者: Bai Na Li Ruixing Gong Zhanli Tan Shoubiao

作者单位: School of Electronics and Information Engineering, Anhui University, Hefei, China;School of Informat School of Electronics and Information Engineering, Anhui University, Hefei, China

会议类型: 国际会议

会议名称: the Second International Conference on Frontiers of Manufacturing and Design Science(第二届制造与设计科学国际会议(ICFMD 2011))

会议地点: 台湾

会议语种:英文

页码: 1332-1337

在线出版日期: 2011-12-11（万方平台首次上网日期，不代表论文的发表时间）