System-Level Simulation and Fabrication of On-Chip Fatigue Bending Test Structure for Micro-Scale Polysilicon Films

摘要：

　　Two kind of on-chip integrated fatigue bending test structures are designed through system-level simulation method based on macromodels to measure the fracture strength and fatigue mechanical properties of polysilicon thin films.The first on-chip fatigue test structure is actuated by V-beam thermal actuator,and the other test structure actuated by electrostatic comb.The static and dynamic analysis was performed by Coventorware Architect module using self-bulid reduced order model described with the MAST hardware language and some other commercial parts from Coventorware parts library.The structural dimension parameters are determined and optimized according to system-level simulation and the computing result has shown that the self-build macromodels and the on-chip integrated test system are efficient and reliable.Two kinds of polysilicon on-chip fatigue bending test structure were fabricated with two-layer polysilicon surface micromachining process in Institute of Microelectronics,Peking University.

关键词： MEMS Model order reduction Fatigue bending test

作者: Le Guan Jiali Gao Qi Liu Bin Li Jinkui Chu

作者单位: Key Laboratory for Dalian University of Technology Precision & Non-traditional Machining of Ministry Key Laboratory for Micro/Nano Technology and System of Liaoning Province, Dalian, CHINA Key Laboratory for Dalian University of Technology Precision & Non-traditional Machining ofMinistry

会议类型: 国际会议

会议名称: 中国微米纳米技术学会第14届学术年会、第3届国际年会暨第6届微米纳米技术“创新与产业化国际研讨与展览会(CSMNT2012 & ICMAN2012)

会议地点: 杭州

会议语种:英文

页码: 1-5

在线出版日期: 2012-11-04（万方平台首次上网日期，不代表论文的发表时间）