Modeling and Simulation of SSN on FPGA Products
Simultaneous switching noise (SSN) and its behavior have recently become more and more critical in IC and other highspeed system designs 12. This is attributed to everincreasing speed, frequency, density, and power, as well as decreasing circuit dimensions and logic levels. The difference in a few mill volts may cause the system to fail. Therefore, it is very important to understand the characteristics of the SSN glitch of an active device for correct system level performance. In this paper, some methods to provide a complete picture of limitation characteristic behavior and its relationship to cause scheme, due to SSN, is demonstrated with FPGA system. Furthermore, model simulation confirms our postulations made on examination of experimental data and validates the methodology practical to SSN assessment in FPGA applications.
Lingzhi Ke Peng Zhou Lei Li
Dept. of Communication and Information System, Wuhan University of Technology, Wuhan, 430070, China Dept. of Communication and Information System, Wuhan University of Technology, Wuhan, 430070, China Shenzhen institute of advance technology, Chinese Academy of Sciences/The Chinese University of Hong
国际会议
北京
英文
407-410
2009-08-10（万方平台首次上网日期，不代表论文的发表时间）