Reuse Issues in SoC Verification Platform

摘要：

As the VLSI design scale shrinks, traditionalverification methods cannot satisfy the SoC verificationrequest, because they do not provide the enough abilityto check the function correctness and cannot ensure theproduct quality. Verification has become the bottleneckof integrated circuit design. A method of bus-basedverification platform is presented and the reusability isimproved greatly. Issues such as verification platformdesign, simulation pattern strategies and reuse, as wellas IP standalone and SoC verification platforms arediscussed. An analysis of the verification platform isperformed from the perspective of the reuse across thedesign cycle, focusing on the IP standalone and the SoCverification platforms.

作者: Rui Wang Wenfa Zhan Guisheng Jiang Minglun Gao Su Zhang

作者单位: Institute of Vlsi Design,Hefei University Of Tech Dept.of Educational Tech.,Anqing Normal College

会议类型: 国际会议

会议名称: The 8th International Conference on Computer Supported Cooperative Work in Design(第八届计算机支持的协同工作设计国际会议)(CSCWD2004)

会议地点: 厦门

会议语种:英文

页码: 685-688

在线出版日期: 2004-05-26（万方平台首次上网日期，不代表论文的发表时间）