A High-Performance CMOS Charge-Pump for Phase-Locked Loops
Inorder to improve the performance of the existing CMOS charge pumps (CPs),a systematical analysis of the existing CMOS CPs is presented. The nonideal effects such as mismatches,switch errorsInCMOS CPs are quantitatively or qualitatively analyzed. Based on the circuit architecture,both classification and comparison are made. An improved CMOS single-ended CP is designedInSMIC 0.18-pro CMOS technology with 1.8-V supply voltage.Inthe CP,the switches are located at the source of the current mirror,and these switches are implemented using transmission gates driven by a couple of complementary clock signals.Inaddition,a large bypass capacitor is added to the CP. These circuits are used to make the CP avoid the switch errors. On the other hand,the charging current IUP and the discharging current IDN are both derived from the same supply-independent reference current source,and a high-gain folded-cascode operational amplifier is used to make the CP evade the sourcing/sinking current mismatch caused by the channel-length modulation effect of the current mirrors. The proposed CP only occupies an active area of 100μm×150μm.Post-simulation results reveal that the proposed CP has a wide output range,from 0.25 V to 1.62V,and near perfect current matching characteristic. The current matching precision is better than 0.0105％.
Jianzheng Zhou Jianzheng Zhou Zhigong Wang
Institute of RF- & OE-ICs,Southeast University,Nanjing 210096,China School of Computer & Information Institute of RF- & OE-ICs,Southeast University,Nanjing 210096,
国际会议
2008 International Conference on Microwave and Millimeter Wave Technology(2008国际微波毫米波技术会议)
南京
英文
839-842
2008-04-21（万方平台首次上网日期，不代表论文的发表时间）