An Automatic Decoder Generator for IA-64 Architecture

摘要：

IA-64 architecture uses 64-bit instruction set, it appliesExplicitlyParallelInstructionComputing(EPIC)technology to improve instruction level parallelism(ILP), brings more difficulties in the analysis and the translation of IA-64 binarycode.Thepaperdescribesthestructureand implementation of a generator, which uses the SLED description of IA-64 instruction set as input.The generator generates C code for an IA-64 instruction decoder automatically. This enables to decrease the developing time of the decoder, to confirm decoders correctness and to improve decoders efficiency. The automatic decoder generator can be used in IA-64 binary translation and reverse engineering.

关键词： decoder generator binary translation reverse engineering

作者: QI Ning ZHAO Rongcai DONG Zehui PANG Jianmin

作者单位: National Digital Switching System Engineering & Technology Research Center Zhengzhou, 450002, P.R China

会议类型: 国际会议

会议名称: 第一届国际计算机新科技与教育学术会议(Proceedings of the First International Conference on Computer Science & Education ICCSE2006)

会议地点: 厦门

会议语种:英文

页码: 39-42

在线出版日期: 2006-07-27（万方平台首次上网日期，不代表论文的发表时间）